This invention relates generally to semiconductor processing, and more particularly to monitoring epitaxial layer washout within such processing.
Patterning is one of the basic steps performed in semiconductor processing. It also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of a deposition process. For example, as shown in FIG. 1A, a layer 104 has been deposited on a substrate 102. After the photolithography process is performed, as shown in FIG. 1B, some parts of the layer 104 have been selectively removed, such that gaps 106a and 106b are present within the layer 104. A photomask, or pattern, is used (not shown in FIG. 1B) so that only the material from the gaps 106a and 106b are removed, and not the other portions of the layer 104. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Such misalignment, or overlay shift, is shown in FIG. 2. The layer 204 may or may not be deposited in a properly aligned configuration on the substrate 202, whereas subsequent deposition layers 206a, 206b, . . . , 206n are misaligned. This is indicated by the reference marks 210a, 210b, . . . , 210n, which are shown in FIG. 2 for illustrative clarity only. The reference marks 210a, 210b, . . . , 210n, should substantially align over the alignment marks 208 of the substrate 202, but they do not.
In comparison to FIG. 2, correctly aligned layers are shown in FIG. 3. The semiconductor wafer 202 has alignment marks 208. The layer 204 is aligned thereupon. Similarly, the layers 206a, 206b, . . . , 206n are deposited upon the layer 204, without any, or with minimal, overlay shift. This is indicated by the reference marks 210a, 210b, . . . , 210n aligning with the alignment marks 208 of the wafer 202.
Specific types of alignment problems can result when using epitaxial layers grown over a semiconductor substrate. Epitaxy is the process in which a thin layer of a single crystal material is deposited on a substrate. Epitaxial growth occurs in such a way that the crystallographic structure of the substrate is reproduced in the growing material, although the conductivity and the doping level of the epitaxial layer can be independent of the underlying substrate layer. Silicon substrates with epitaxial layers are commonly used in complementary metal-oxide silicon (CMOS) semiconductor devices, bi-CMOS devices, high-voltage devices, and bipolar devices.
FIGS. 4A, 4B, and 4C show the alignment problems that can occur within a pattern in an epitaxial layer relative to the pattern in a substrate layer. In FIG. 4A, pattern shift has occurred. The pattern 406 in the substrate layer 402 has shifted to the right as the pattern 408 in the epitaxial, or epi, layer 404. In FIG. 4B, pattern distortion has occurred. The pattern 436 in the substrate layer 438 has become distorted as the pattern 438 in the epi layer 434. That is, the pattern 438 is smaller in width than the pattern 436 is. In FIG. 4C, pattern washout has occurred. The pattern 466 in the substrate layer 462 has washed out as the pattern 468 in the epi layer 464. These sorts of alignment problems can occur because of non-ideal deposition of the epi layers, and/or because of other improper processing. The patterns of FIGS. 4A, 4B, and 4C can be alignment marks, used for alignment in the subsequent processing of the epi layers and other layers.
When the alignment problems of FIGS. 4A, 4B, and 4C occur, adjustment must be made to the position of features on subsequent layers in order to compensate for the errors introduced in the epi layers. Selecting the correct amount of adjustment, however, is usually complicated by the fact that the effects are dependent on such varying factors as substrate orientation, deposition rate, deposition temperature, and silicon source. Furthermore, in the case of pattern washout of FIG. 4C in particular, subsequent processing performed relative to the epi layer 464 will likely fail, because the semiconductor processing equipment will most likely not be able to align with the washed-out pattern 468. This alignment failure may be corrected by instead performing manual alignment, but this is a time-intensive and costly process.
Therefore, there is a need to be able to monitor epitaxial layer washout of alignment and other patterns. Such monitoring should be able to yield whether washout has occurred, so that it can be determined whether a given semiconductor wafer lot must be scrapped. Furthermore, such monitoring should be able to yield at what feature size washout has occurred, so that only the minimum number of semiconductor wafers is scrapped. For these and other reasons, there is a need for the present invention.
The invention relates to a pattern for monitoring epitaxial layer washout. The pattern includes first and second sub-patterns. The first sub-pattern has a shape and defines one or more minimum dimensions. Obfuscation of the first sub-pattern means that epitaxial washout has occurred at least for dimensions equal to or less than the minimum dimensions. The second sub-pattern has the same shape of the first sub-pattern, but defines one or more maximum dimensions. Obfuscation of the second sub-pattern means that epitaxial washout has occurred for dimensions equal to or less than the maximum dimensions.
The invention provides for advantages over the prior art. A series of sub-patterns may have decreasing dimensions at regular intervals. By proceeding down the series of sub-patterns, and determining the first sub-pattern of the series that is not clearxe2x80x94that is, which is obfuscatedxe2x80x94a semiconductor technician can easily determine at which dimensions epitaxial layer washout has occurred. These dimensions are those that are equal to or less than the dimensions of the first sub-pattern of the series that is obfuscated. These dimensions can be referred to as the washout values for the epitaxial layer, and can include different horizontal and vertical dimensions, and hence washout values.
Still other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.